1. Field of the Invention
The present invention relates to high-density monolithic memories and, in particular, to a more effective and fast the utilization of hierarchical redundancy schemes to convert a partially functional memory chip into a fully functional chip thereby improving the overall performance of functional chips on a semiconductor wafer.
2. Discussion of the Related Art
Today's highly advanced computer and electronic systems require high speed and high density memory chips. The increase in the density of the memory chip results in the complexity of the manufacturing processes used to manufacture the memory chips. Consequently, the possibility of defective memory cells or rows of memory cells increases. The defect density resulting from the integrated circuit fabrication process limits the functional yield. While an increasing amount of attention has been focused on controlling the fabrication process to limit defect density, as chip geometries shrink and chip size increases, it becomes increasingly difficult to control the process sufficiently to achieve a high natural functional yield.
A number of techniques, such as redundancy schemes, have been utilized to increase the functional yield of memory devices. A commonly used redundancy scheme provides spare rows and/or columns in the memory array that can be used to replace defective bits, rows or columns.
During the fabrication of a monolithic memory device, process defects can disable single or multiple cells, rows and/or columns in the array. Typically to overcome these defects, spare or redundant rows and/or redundant columns are provided. These spare memory cells are then utilized to replace defective cells, rows and/or columns. If there is a defect in a given section of the memory array, causing a normal row or a normal column or a single bit to fail, then that particular row or column or bit is permanently disabled and is replaced by a redundant row or a redundant column. The obvious limitation on the number of redundant rows and/or columns is the acceptable chip size and cost.
Each redundant row or column is associated with one fuse or a set of fuses. When the particular fuse or set of fuses is/are blown, the redundant row or column is used instead of the defective row or column. Referring now to FIG. 1, a schematic of a conventional fuse arrangement is shown. Fuse arrangement 10 includes multiple sub arrangements 12-1 through 12-n. Each of the sub arrangements 12-1 through 12-1 includes a series of fuses 14 that are connected to the supply voltage Vcc through transistor 16 and to ground through a transistor 18 connected in series with a resistors 20. Each of the sub arrangements 12-1 through 12-n has a respective output O1 through On that is used individually or in combination with the output of other sub arrangements to select a redundant row or column. If a redundant row or column is selected to replace a defective row or column of memory cell, the corresponding fuse or set of fuses will be blown.
In operation, the external address is decoded by the decoding circuitry in a memory chip. The decoded address also points to an specific fuse or a set of fuses. For example, a 16 bit address can be divided to four 4-bit address bits, with each 4-bit representing an address to one fuse. In the arrangement of FIG. 1, each fuse would belong to a separate sub arrangement. Thus, in this example, each redundant row or column is associated with four fuse 14. Next, the addressed fuses 14 are examined to determine whether they are blown, signifying the fact that the corresponding row or column is selected, or not.
To examine the particular fuse, the associated transistor 18 is turned on. At the same time all the other transistors 18 in the sub arrangement 12-1, for example, are turned off. The voltage at the output node O1 is then examined. If the fuse is blown, then the current path through the fuse 14, transistor 18, and resistor 20 is open, thus the voltage at output O is at Vcc level. On the other hand, if the fuse is not blown, then the current path through the fuse 14, transistor 18, and resistor 20 is established and the voltage at the output node O1 will be at ground level. Thus, to determine whether a redundant row or column is selected the voltage at output of sub arrangements associated with the row or column should be at Vcc level. If one voltage is not at the Vcc level, this signifies that the row or column is not selected.
The internal circuitry of the memory chip performs the above process for every new address. This requires that the output of the each sub arrangements 12-1 through 12-n be set at the initial voltage level (in this case Vcc) before every comparison process. After every comparison, the next comparison can only begin after the voltage at the output of all sub arrangements 12-1 through 12-n are charged up to the Vcc level. Obviously, the output of the sub arrangement with a blown fuse need not be charged to Vcc level since it is at that level already. The charging process reduces the overall operational speed of the memory. In an environment where high-speed memory chips are required, this can be problematic.
The second problem is the time required for the internal circuitry to decode the input address and to determine whether it must access a memory cell in a regular row and column intersection or a redundant row and column intersection.
In view of the above, there is a need for a redundancy scheme that overcomes these problems.